1. Field of the Invention
This invention relates to a manufacturing method of a semiconductor device, specifically to a manufacturing method of a semiconductor device having an opening in a semiconductor substrate.
2. Description of the Related Art
It is known that a via hole (opening) is formed to penetrate through a semiconductor substrate from one of principal surfaces of the semiconductor substrate to the other and a conductive material (metal such as aluminum, copper, tungsten and titanium tungsten) serving as a wiring is formed in the via hole so that conductors disposed on both of the principal surfaces are electrically connect with each other.
Bosch process has been known as one of methods to form the via hole. The Bosch process is used to produce a deep vertical trench in the semiconductor substrate and consists of two periodically alternating processes, which are a plasma etch process in which a surface of the semiconductor substrate is plasma etched isotropically using a SF6 gas and a plasma deposition process in which carbon polymers are deposited as a protection film using a C4F8 gas on a sidewall of the trench formed by the plasma etch process.
When the plasma etch process is performed by the Bosch process, a via hole 101 is formed to penetrate a semiconductor substrate 100, as shown in FIG. 14. It is known, however, that rough shapes (hereafter referred to as scallops 102) are caused on a surface of a sidewall of the via hole 101 at the same time. The scallops 102 result from the isotropic etching in the plasma etch process.
The technology mentioned above is described in Japanese Patent Application Publication No. 2006-12889, for example.
When the surface of the sidewall of the via hole 101 is turned to the scallops 102, it is difficult to form a desired film (an insulation film or a barrier layer, for example) homogeneously on the sidewall of the via hole 101, thereby causing a problem that is reduction in yield and reliability of the semiconductor device.
To describe concretely, when an insulation film 103 is formed on the sidewall of the via hole 101 and a barrier layer 104 (a titanium layer, a titanium-tungsten layer, a tantalum layer or a tantalum nitride layer, for example) or a conductive material serving as a wiring is to be deposited on the insulation film 103 by sputtering as shown in FIG. 15A, for example, there has been a region to which sputtered particles do not reach sufficiently because of the scallops 102, thereby making the sputtered layer uneven in thickness and insufficient in coverage. Particularly when an aspect ratio (height/aperture diameter) of the via hole 101 is high, forming a homogeneous film becomes even more difficult, resulting in reduced functionality of the barrier layer 104 and the wiring.
Similarly, when the barrier layer 104 or the conductive material serving as the wiring is formed by CVD (Chemical Vapor Deposition), a reaction gas does not reach evenly to the sidewall of the via hole 101 because of the scallops 102, and there has been a region where the layer deposited by CVD becomes insufficient in coverage.
In addition, there is a case in which the film is formed thicker than usually required in order to avoid the insufficient coverage, which causes problems of reduced productivity and an excessive thickness of the film in a specific region.
Also, the scallops 102 have sharp edges which are to be reflected in a film formed in the via hole 101 in a later process step. As a result, when the insulation film 103, the barrier layer 104 and a seed layer 105 that serves as a plating electrode are formed consecutively in the via hole 101 and a through-hole electrode 106 is formed in the via hole 101 by plating as shown in FIG. 15B, electric charge convergence is caused at the sharp edges 107 of the seed layer 105 in the plating process. Then a material (copper or aluminum, for example) forming the through-hole electrode 106 grows abnormally at the sharp edges 107 to form abnormally grown portions 108 as shown in FIG. 15B. Since the abnormally grown portions 108 touch the material forming the through-hole electrode 106 on the opposite side when they grow further, appropriate plating is not performed and there are caused problems that the through-hole electrode 106 is disconnected and a void is caused in the through-hole electrode 106.
Reducing etch rate in the Bosch process could suppress generation of the scallops 102. However, it causes a problem of reduced productivity.
This invention is directed to offer a manufacturing method of a semiconductor device, which makes it possible even when the scallops are caused in the process to form the via hole using the Bosch process that practically homogeneous films are formed in the via hole in later process steps.